1. Field of the Invention
The present invention relates to a semiconductor memory device employing a layered bit line system, in which main bit lines provided over sub bit lines are selectively connected to the sub bit lines. More specifically, the present invention relates to a semiconductor memory device in which a load on the main bit line is reduced, thereby realizing high-speed access.
2. Description of the Related Art
U.S. Pat. No. 5,621,697 discloses a semiconductor memory device employing a layered bit line system.
FIG. 6 shows a semiconductor memory device 100 employing the conventional layered bit line system.
The semiconductor memory device 100 includes a plurality of banks BNK100, BNK101 and BNK102.
The banks BNK100, BNK101 and BNK102 each include a plurality of memory cells M, a plurality of sub bit lines SB, a plurality of wordlines WL, a first bank select line BL, and a second bank select line BS.
The banks BNK100 and BNK101 share sub bit lines SB11, SB15 and SB19. The banks BNK101 and BNK102 share sub bit lines SB13 and SB17.
U.S. Pat. No. 5,202,848 discloses another semiconductor memory device employing a layered bit line system.
FIGS. 7 and 8 show another semiconductor memory device 200 employing the conventional layered bit line system.
The semiconductor memory device 200 includes a plurality of banks BNK0, BNK1 and BNK2, auxiliary conduction regions BB11-BB22, a plurality of main bit lines MB1-MB4, and a plurality of contacts CT11-CT22. Specifically, the first bank BNK1 includes a plurality of sub bit lines SB11-SB17, and the second bank BNK2 includes a plurality of sub bit lines SB21-SB27. The plurality of sub bit lines SB11-SB17 included in the first bank BNK1 are electrically isolated from the plurality of sub bit lines SB21-SB27 included in the second bank BNK2.
Switches TB15 and TB16 of the first bank BNK1 and switches TB25 and TB26 of the second bank BNK2 are coupled to the auxiliary conduction region BB21. Specifically, the switch TB15 is coupled to the sub bit line SB11; the switch TB16 is coupled to the sub bit line SB13; the switch TB25 is coupled to the sub bit line SB21; and the switch TB26 is coupled to the sub bit line SB23. That is, in the semiconductor memory device 200, four switches (e.g., the switches TB15, TB16, TB25, and TB26) are directly coupled to a single auxiliary conduction region (e.g., the auxiliary conduction region BB21).
In the semiconductor memory device 100 (FIG. 6), first switches TB12 and TB21 and a second switch TC16 are turned ON in order to read data stored in a memory cell M4. A source electrode and a drain electrode of the memory cell M4 are connected to the main bit lines MB2 and MB3, respectively. At this time, the main bit line MB2 is connected to the sub bit line SB13 which is commonly included in both the bank BNK101 and the bank BNK102 through the first switch TB21, and the main bit line MB3 is connected to the sub bit line SB15 which is commonly included in both the bank BNK100 and the bank BNK101 through the first switch TB12. Thus, a load increases when data is read out, whereby the semiconductor memory device 100 cannot read data at a high speed.
In the semiconductor memory device 200, since four switches are directly coupled to a single auxiliary conduction region, a capacity between a gate and a drain of a switch, or a junction capacity between a substrate and a drain increases. Therefore, data cannot be read at a high speed.